The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device performing a data access operation by replacing a repair-expected memory cell among normal memory cells with a normal redundancy memory cell.
In general, as a degree of integration of a semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) device is increasing rapidly, tens of millions of memory cells are being included in one semiconductor memory device. These memory cells construct a memory cell array where the memory cells are uniformly arranged and a group of memory cell arrays is referred to as a memory cell matrix. The semiconductor memory device includes a plurality of memory cell matrixes.
If even one of the memory cells is failed, the semiconductor memory device may not perform a desired operation. However, as the technology of fabricating the semiconductor memory device is being developed, a small amount of memory cells is only failed stochastically and thus it may be very ineffective to dispose the semiconductor memory device as a defective product by the failure of few memory cells when considering the product yield. In order to make up for the failure, separately designed redundancy memory cells are further employed in the semiconductor memory device in addition to normal memory cells. Therefore, if normal memory cells are failed, the failed normal memory cells are replaced with the redundancy memory cells. Hereinafter, a memory cell of the normal memory cells that is failed and thus should be replaced with a redundancy memory cell is referred to as ‘a repair-expected memory cell’.
Meanwhile, a memory cell structure of the semiconductor memory device can be classified into a folded bit line structure and an open bit line structure and they have following differences.
First of all, the folded bit line structure includes a bit line, e.g., a positive bit line, where data is driven and a bit line, e.g., a negative bit line, that is a standard when performing an amplifying operation on the data, wherein the positive bit line and the negative bit line are disposed in the same memory cell matrix on the basis of a bit line sense amplifier disposed in a core region of the semiconductor memory device. Therefore, the same noise is reflected on the positive bit line and the negative bit line and these noises offset each other. Through this offset operation, the folded bit line structure guarantees a stable operation against the noise. In the meantime, the open bit line structure includes a positive bit line and a negative bit line that are disposed in different memory cell matrixes on the basis of a bit line sense amplifier. Therefore, a noise occurring in the positive bit line is different from that occurring in the negative bit line and thus the open bit line structure may be weak to the noise.
Furthermore, while a unit memory cell in the folded bit line structure is designed in the structure of 8F2, a unit memory cell in the open bit line structure is designed in the structure of 6F2. The unit memory cell structure becomes a factor of determining the size of the semiconductor memory device. Accordingly, for the same amount of data storage, a semiconductor memory device having the open bit line structure can be designed smaller in size than a semiconductor memory device having the folded bit line structure.
FIG. 1 illustrates a cell array structure of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes normal memory cell arrays 110 and 130 where a plurality of memory cells is arranged. For illustration purposes, an upper part on the basis of a bit line sense amplifying block (SA) 170 is referred to as an even memory cell matrix and a lower part on the basis of the bit line sense amplifying block 170 is referred to as an odd memory cell matrix.
The even memory cell matrix and the odd memory cell matrix include a plurality of word lines (WL) corresponding to the memory cell arrays, respectively. Therefore, one corresponding word line is activated in a data access operation, e.g., a reading/writing operation. Each of bit line sense amplifiers included in the bit line sense amplifying block 170 is connected to a corresponding positive bit line BLT and a corresponding negative bit line BLB, and senses and amplifies a voltage level difference of the positive bit line BLT and the negative bit line BLB. The amplified data are transferred through local input/output lines LIO(T/B)0 and LIO(T/B)2.
For the reference, a bit line sense amplifying block (not shown) playing the same role as the bit line sense amplifying block 170 does is disposed at an upper side of the even memory cell matrix, and the negative bit line BLB disposed in the even memory cell matrix is connected to the bit line sense amplifying block disposed at the upper side of the even memory cell matrix. Moreover, a bit line sense amplifying block (not shown) is also disposed at a lower side of the odd memory cell matrix, and the positive bit line BLT disposed in the odd memory cell matrix is connected to the bit line sense amplifying block disposed at the lower side of the odd memory cell matrix.
Hereinafter, a data access operation will be roughly described with reference to the cell array structure of FIG. 1.
In the data access operation, if one word line WL is activated, a normal memory cell array corresponding to the activated word line WL is actuated. That is, each normal memory cell corresponding to the activated word line WL is actuated and data stored in the actuated normal memory cell is transferred to a corresponding bit line.
If a word line WL disposed in the even memory cell matrix is activated, data stored in each normal memory cell connected to the activated word line WL is transferred to the bit line sense amplifying block 170 through the positive bit line BLT, wherein the negative bit line BLB disposed in the odd memory cell matrix is used as a reference bit line when sensing and amplifying the data transferred through the positive bit line BLT. Meanwhile, if a word line WL disposed in the odd memory cell matrix is activated, data stored in each normal memory cell connected to the activated word line WL is transferred to the bit line sense amplifying block 170 through the negative bit line BLB, wherein the positive bit line BLT disposed in the even memory cell matrix is used as a reference bit line when sensing and amplifying the data transferred through the negative bit line BLB.
In the even memory cell matrix, logical data may have the same polarity as that of physical data. That is, a memory cell connected to the positive bit line BLT of the even memory cell matrix physically stores a value corresponding to a logic high to store logical data of a logic high and a value corresponding to a logic low to store logical data of a logic low. On the other hand, in the odd memory cell matrix, the polarity of logical data is different from that of physical data. That is, a memory cell connected to the negative bit line BLB of the odd memory cell matrix physically stores a value corresponding to a logic low to store logical data of a logic high and a value corresponding to a logic high to store logical data of a logic low.
In the meantime, redundancy memory cell arrays 150 are prepared to be replaced with repair-expected memory cells that may occur in the normal memory cell arrays 110 and 130 and each of the redundancy memory cell arrays 150 is connected to a redundancy word line RWL. As described above, the redundancy memory cell arrays 150 are designed separately from the normal memory cell arrays 110 and 130 and thus they are not included in a memory cell matrix. Herein, as one example, the redundancy memory cell arrays 150 are designed to have a structure similar to those of the even memory cell matrix. Therefore, in the redundancy memory cell arrays 150, logical data has the same polarity as that of physical data, which is a characteristic of the even memory cell matrix.
Hereinafter, an operation of repairing a repair-expected memory cell will be described with reference to the structure of FIG. 1. For illustration purposes, it is assumed that the normal memory cell arrays 110 and 130 include repair-expected memory cells.
In the data access operation, if addresses corresponding to the repair-expected memory cell are coupled thereto, the semiconductor memory device does not activate a word line WL corresponding to the addresses but activate a redundancy word line RWL corresponding to the addresses. Therefore, the data access operation corresponding to the addresses is performed in the redundancy memory cells included in the redundancy memory cell arrays 150 that operate normally instead of the repair-expected memory cells included in the normal memory cell arrays 110 and 130. In other words, in the conventional semiconductor memory device, in case the even memory cell matrix and the odd memory cell matrix include the repair-expected memory cells, each of the repair-expected memory cells is replaced with a corresponding one of the redundancy memory cell arrays 150 (as denoted by using arrows with dot lines).
Meanwhile, the semiconductor memory device performs various tests before the shipment thereof. Among those tests, there is a disturb test of providing stress to a memory cell.
FIG. 2 illustrates a view of explaining data coupled to a memory cell in the disturb test.
Referring to FIG. 2, in the disturb test, ‘0’ data corresponding to a logic low is inputted to a test-target memory cell and ‘1’ data corresponding to a logic high is inputted to memory cells adjacent to the test-target memory cell. Therefore, the test-target memory cell where the ‘0’ data is coupled is stressed by the ‘1’ data coupled to the adjacent memory cells thereof.
Referring back to FIG. 1, the disturb test is performed by sequentially supplying a data pattern such as that in FIG. 2 to the memory cell array. The normal memory cell arrays 110 of the even memory cell matrix and the normal memory cell arrays 130 of the odd memory cell matrix do not have any difficulties when performing the disturb test. However, in case of the redundancy memory cell arrays 150, the disturb test may not be performed therein. For instance, in the disturb test where the data pattern such as that in FIG. 2 should be provided, the redundancy memory cell array to be repaired corresponding to the odd memory cell matrix should be provided with data having the polarity opposite to that of the odd memory cell matrix. In this case, it may be difficult to perform the disturb test with a desired data pattern. Therefore, although the redundancy memory cell arrays 150 are designed weak to the stress, it may not be detected. As a result, in case the repair-expected memory cell should be replaced with the redundancy memory cell, it may be difficult to secure a smooth data access operation. That is, there may be a problem of degrading the reliability of the semiconductor memory device.